In standard complementary metal oxide semiconductor (CMOS) devices, polysilicon is typically the standard gate material. The technology of fabricating CMOS devices using polysilicon gates has been in a constant state of development, and is now widely used in the semiconductor industry. One advantage of using polysilicon gates is that they can sustain high temperatures. However, there are also some problems associated with using a polysilicon gate. For example, due to the poly-depletion effect and relative high electrical sheet resistance, polysilicon gates commonly used in CMOS devices are becoming a gating factor in chip performance for channel lengths of 0.1 micron and below. Another problem with polysilicon gates is that the dopant in the polysilicon gate, such as boron, can easily diffuse through the thin gate dielectric causing further degradation of the device performance.
Another problem with polysilicon gates which include a dielectric material having a dielectric constant that is greater than that of silicon dioxide is that during inversion the polysilicon gate undergoes a threshold voltage or flatband shift that shifts those values from ideal values to non-ideal values.
In order to avoid the problems with polysilicon gates, it has been suggested to form a single metal beneath the polysilicon gate. That is, in current processing a thin metal layer for both the pFET and the nFET device is formed beneath a polysilicon gate electrode. During device processing, which includes thermal techniques above 1000° C., polysilicon appears to interact with the thin metal changing the workfunction and therefore the threshold voltages of the devices. In particular, hydrogen from the silane as well as silicon may diffuse into the metal layer forming hydrides or silicides which have a mid-gap workfunction. For example, during high temperature annealing, a polysilicon/metal gate stack becomes mid-gap rather than a solution for a pFET or an nFET.
In view of the above, there is a continued need for providing a semiconductor structure in which the nFETs are engineered to include a metal gate which maintains n-type behavior, while the pFETs are engineered to include a metal gate which maintains p-type behavior.